This Application claims priority to British Patent Application No. 0102173.2 filed on Jan. 27, 2001.
The present invention relates to a direct memory access controller for accessing circular buffers of memory in a computer system and to a method of operating a computer system comprising such a direct memory access controller.
Conventional computer systems have been based around the combination of a processor (typically a microprocessor) and internal or external memory. In order to reduce the load on the microprocessor, so-called direct memory access (DMA) controllers have been introduced. These are typically integrated onto the same chip as the processor.
DMAs comprise hard-wired logic for performing memory access operations. A computer system architecture comprising a DMA controller 1 is illustrated in FIG. 1. Typically, in order to perform an access operation for a block of data, a microprocessor 2 stores in respective registers: the start (or xe2x80x9csourcexe2x80x9d) address of the memory block from which the data is to be transferred; the start (or xe2x80x9cdestinationxe2x80x9d) address of the block of memory to which the data is to be transferred; and the size of the data block to be transferred. Typically, one of the source and destination locations is on a memory 3 located on the same chip as the processor and DMA controller, with the other of the source and destination locations being on an external memory 4. However, one or both of the locations may be a processor register or an external memory mapped device.
Queuing systems and data buffers are often implemented in memory as circular buffers in order to make efficient use of memory. A circular buffer occupying 16 bytes of memory space is illustrated in FIG. 2. A data sequence in a circular buffer may be wrapped around from the top of the buffer to its start.
Performing a DMA access to a circular buffer remains processor intensive, in that the microprocessor must calculate whether or not the top of the buffer will be reached during any given access operation, i.e. the block size remaining to be accessed by the DMA will not have decremented to 1 by the time that the top of wrap around (or rollover) condition is reached. Considering the 16 byte circular buffer of FIG. 1, assume that the microprocessor wishes to access a data block which is 10 bytes long, and that the starting point from the transfer is memory address 9. The microprocessor performs a check, prior to instructing the DMA controller to perform the access, to see if the rollover condition will occur during the access. As a rollover will occur, the microprocessor must split the DMA access into two consecutive transfers. During the first access, the DMA controller""s registers will be set to:
This causes the seven bytes indicated in FIG. 2 to be accessed. In the second access, the DMA controller""s registers will be set to:
This causes the three bytes indicated in FIG. 3 to be accessed.
In order to detect that a rollover condition will occur, the microprocessor incurs additional processing overheads. Additional processing overheads also arise from having to compute two source addresses, two destination addresses, and two transfer block sizes.
It is an object of the present invention to overcome the above noted disadvantages of known computer systems. This and other objects are achieved by sending from the microprocessor to the DMA controller a value identifying the size of the circular buffer.
According to a first aspect of the present invention there is provided a method of accessing a circular buffer within a memory of a computer system comprising a processor and a direct memory access (DMA) controller, the method comprising:
notifying the DMA controller of the address of the start of a block of memory to be accessed, the size of the memory block, and the size of the circular buffer;
at the DMA controller, identifying a base address and a rollover address of the circular buffer; and
accessing the circular buffer starting at the start address, continuing until the rollover address is reached, and continuing the access from said buffer base address until the end of the block is reached.
Embodiments of the present invention require a processor to transfer only a single transfer instruction to the DMA controller for each circular buffer access. Moreover, the task of computing the rollover address and (optionally) the base address of the buffer is transferred from the processor to the DMA controller. The circular buffer accessed may be a source buffer or a destination buffer for a data transfer.
Preferably, the start address of the block to be accessed is written to a dedicated register of the DMA controller by the processor. The circular buffer size may also be written to this same register.
Preferably, a value representing the circular buffer size is transferred from the processor to the DMA controller. This value may identify a unique one of a set of buffer sizes. For example, a set of eight buffer sizes may be uniquely identified by a three bit value.
More preferably, the base address of each of the circular buffers in use is specified as being located on a power of 2 boundary, or a predefined distance from a power of 2 boundary. This architecture allows the base address of a circular buffer to be determined using certain of the most significant bits of a source/destination address associated with an access request to that buffer, and setting the remaining least significant bits to 0. The number of bits set to zero corresponds to the size of the circular buffer.
According to a second aspect of the present invention there is provided a method of transferring a block of data from a first to a second circular buffer of a computer system comprising a processor and a direct memory access (DMA) controller, the method comprising:
notifying the DMA controller of the source and destination addresses for the transfer in the first and second buffers respectively, the sizes of the circular buffers, and the size of the data block to be transferred;
at the DMA controller, identifying respective base and rollover addresses of the circular buffers; and
reading data from the first circular buffer starting at the source address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached; and
writing data to the second circular buffer starting at the destination address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached.
It will be appreciated that the steps of reading and writing may be carried out simultaneously, reading one word from the first buffer and writing that word to the second buffer, before reading the next word from the first buffer. Alternatively, data may be read and written in sub-blocks, or as an entire block.
According to a third aspect of the present invention there is provided a direct memory access (DMA) controller for accessing a circular buffer within a memory of a computer system, the DMA controller comprising:
input means for receiving from a processor an instruction to access a block of a circular buffer;
a first register for receiving a start address within said buffer and a value defining the size of the circular buffer;
a second register for receiving a value defining the size of a block of the circular buffer to be accessed;
means for identifying a base address and a rollover address of the circular buffer; and
means for accessing the circular buffer starting at the start address, continuing until the rollover address is reached, and continuing the access from said buffer base address until the end of the block is reached.
According to a fourth aspect of the present invention there is provided a direct memory access (DMA) controller for transferring a block of data from a first to a second circular buffer of a computer system, the DMA controller comprising:
a first register for receiving a source address within said first buffer and a value defining the size of the first circular buffer;
a second register for receiving a destination address within said second buffer and a value defining the size of the second circular buffer;
a third register for receiving a value defining the size of the data block to be transferred;
means for identifying respective base and rollover addresses of the circular buffers; and
means for reading data from the first circular buffer starting at the source address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached, and writing data to the second circular buffer starting at the destination address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached.
According to a fifth aspect of the present invention there is provided a computer system comprising:
a processor;
a DMA controller according to the third or fourth aspects of the present invention;
a memory; and
address and data buses interconnecting the processor, DMA controller, and memory.